[verilog] wb_block 테스트벤치

`timescale 1ns/1ps
module tb_wb_block;
reg  clk;
reg rstn;

//////////////
reg wb_start;
wire wb_done;

// between directory
reg [31:0] wb_address;
reg [(32*8)-1:0] wb_cache_line;

// between sram
wire req_valid;
wire [31:0] req_data;
wire req_wren;
wire [31:0] req_address;
reg req_ready;

//////////


initial begin
    clk = 1;
    forever begin
        #10 clk = ~clk;
    end
   end

   wb_block u1(
    .wb_start(wb_start),
    .wb_done(wb_done),

    // between directory
    .wb_address(wb_address),
    .wb_cache_line(wb_cache_line),

    // between sram
    .req_valid(req_valid),
    .req_data(req_data),
    .req_wren(req_wren),
    .req_address(req_address),
    .req_ready(req_ready),

	.clk(clk),
  	.rstn(rstn)

   );

   //------여기서 부터 아래 선까지는 waveform을 보기위한 파일을 만드는 코드이다.---- 
   initial
   begin
      $dumpfile("test_out.vcd");
      $dumpvars(-1,u1);  
   end
   //------------------------------------------------------------------------------

    initial begin
    
    rstn = 1;
    wb_start = 0;
    wb_address = 0;
    wb_cache_line = 0;
    req_ready = 0;
 
    #1 rstn = 0;
    #1 rstn = 1;
    
    wb_address = 32'h00000000;
    wb_cache_line = 256'h12345678_23456789_34567890_45678901_56789012_67890123_78901234_89012345;
    wb_start = 1;
    req_ready = 1;
    
    #40 req_ready = 0;
    #40 req_ready = 1;
    #40 req_ready = 0;
    #40 req_ready = 1;
    #40 req_ready = 0;
    #40 req_ready = 1;
    #40 req_ready = 0;
    #40 req_ready = 1;


  end

     initial
   #800 $finish;

endmodule