// Code your design here module pulse_counter( input source, output reg [3:0] cnt, input clk, input rstn ); reg internal_cnt; always @(posedge clk or negedge rstn) begin if (!rstn) begin internal_cnt = 0; cnt = 0; end else begin if (source == 0) begin internal_cnt = 1; end else begin if (internal_cnt == 1) begin cnt = cnt+1; internal_cnt = 0; end else begin cnt = cnt; internal_cnt = 0; end end e..