[verilog] 클럭에 동기화된 펄스카운터 테스트벤치

// Code your testbench here
// or browse Examples
module tb_top;
   reg  clk;
   reg source;
  wire [3:0] cnt;
   reg rstn;
  
  initial begin
    clk = 1;
    forever begin
      #10 clk = ~clk;
    end
  end
  
  
  // Instantiate device under test
  pulse_counter u1(.source(source),
                   .cnt(cnt),
                   .clk(clk),
                   .rstn(rstn));
  
  initial begin
    $dumpfile("dump.vcd");
    $dumpvars(1, tb_top);
    
    rstn = 1;
    source = 0;
 
    #1 rstn = 0;
    #1 rstn = 1;
    
    #1 source = 1;
    #20 source = 0 ;
    #20 source = 1 ;
    #20 source = 0 ;
    #20 source = 0 ;
    #20 source = 0 ;
    #20 source = 1 ;
    #20 source = 0 ;
    #20 source = 1 ;
    #20 source = 0 ;
    #20 source = 1 ;
  end

  initial
#200 $finish;
  
endmodule