[verilog] wb_block 코드

// Code your design here
module wb_block(
	// between controller
    input wb_start,
    output reg wb_done,

    // between directory
    input [31:0] wb_address,
    input [(32*8)-1:0] wb_cache_line,

    // between sram
    output reg req_valid,
    output reg [31:0] req_data,
    output reg req_wren,
    output reg [31:0] req_address,
    input req_ready,

	input clk,
  	input rstn
);
  
  	// state
    localparam IDLE = 1'b0;
    localparam EXEC = 1'b1;

    // reg
    reg current_state, next_state;
    reg [3:0] captured_cnt;

    // wire
    wire [3:0] cnt;

    // pulse_counter
    pulse_counter u1(.source(current_state), .cnt(cnt), .clk(clk), .rstn(rstn));

    // FF for state
    always @(posedge clk or negedge rstn) begin
        if (!rstn) begin
            current_state <= 0;
        end
        else begin
            current_state <= next_state;
        end
    end

    // ff for captured_cnt
    always @(posedge clk or negedge rstn) begin
        if (!rstn) begin
            captured_cnt <= 0;
        end
        else begin
            if (current_state == IDLE) begin
                captured_cnt <= cnt;
            end
            else begin
                captured_cnt <= captured_cnt;
            end
        end
    end

    // next_state
    always @(*) begin
        case (current_state)
            IDLE : begin
                if (wb_start == 1 && cnt < 8) begin
                    next_state = EXEC;
                end
                else begin
                    next_state = IDLE;
                end
            end
            EXEC : begin
                if (req_ready == 0) begin
                    next_state = EXEC;
                end
                else begin
                    next_state = IDLE;
                end
            end
        endcase
    end
  
    // output
    always @(*) begin
        case (current_state)
            IDLE : begin
                req_valid = 0;
            end
            EXEC : begin
                req_valid = 1;
                req_address = wb_address + captured_cnt * 4;
                req_data = wb_cache_line[captured_cnt*32 +: 32];
                req_wren = 1;
            end
        endcase
    end

    // done
    always @(*) begin
        if(wb_start == 1 && cnt >= 8) begin
            wb_done = 1;
        end
        else begin
            wb_done = 0;
        end
    end

endmodule