기록보관소

// Code your design here module pulse_counter( input source, output reg [3:0] cnt, input clk, input rstn ); reg internal_cnt; always @(posedge clk or negedge rstn) begin if (!rstn) begin internal_cnt = 0; cnt = 0; end else begin if (source == 0) begin internal_cnt = 1; end else begin if (internal_cnt == 1) begin cnt = cnt+1; internal_cnt = 0; end else begin cnt = cnt; internal_cnt = 0; end end e..

// Code your testbench here // or browse Examples module tb_top; reg clk; reg source; wire [3:0] cnt; reg rstn; initial begin clk = 1; forever begin #10 clk = ~clk; end end // Instantiate device under test pulse_counter u1(.source(source), .cnt(cnt), .clk(clk), .rstn(rstn)); initial begin $dumpfile("dump.vcd"); $dumpvars(1, tb_top); rstn = 1; source = 0; #1 rstn = 0; #1 rstn = 1; #1 source = 1; ..