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`timescale 1ns/1ps module tb_wb_block; reg clk; reg rstn; ////////////// reg wb_start; wire wb_done; // between directory reg [31:0] wb_address; reg [(32*8)-1:0] wb_cache_line; // between sram wire req_valid; wire [31:0] req_data; wire req_wren; wire [31:0] req_address; reg req_ready; ////////// initial begin clk = 1; forever begin #10 clk = ~clk; end end wb_block u1( .wb_start(wb_start), .wb_do..

// Code your design here module wb_block( // between controller input wb_start, output reg wb_done, // between directory input [31:0] wb_address, input [(32*8)-1:0] wb_cache_line, // between sram output reg req_valid, output reg [31:0] req_data, output reg req_wren, output reg [31:0] req_address, input req_ready, input clk, input rstn ); // state localparam IDLE = 1'b0; localparam EXEC = 1'b1; /..

// Code your design here module pulse_counter( input source, output reg [3:0] cnt, input clk, input rstn ); reg internal_cnt; always @(posedge clk or negedge rstn) begin if (!rstn) begin internal_cnt = 0; cnt = 0; end else begin if (source == 0) begin internal_cnt = 1; end else begin if (internal_cnt == 1) begin cnt = cnt+1; internal_cnt = 0; end else begin cnt = cnt; internal_cnt = 0; end end e..

// Code your testbench here // or browse Examples module tb_top; reg clk; reg source; wire [3:0] cnt; reg rstn; initial begin clk = 1; forever begin #10 clk = ~clk; end end // Instantiate device under test pulse_counter u1(.source(source), .cnt(cnt), .clk(clk), .rstn(rstn)); initial begin $dumpfile("dump.vcd"); $dumpvars(1, tb_top); rstn = 1; source = 0; #1 rstn = 0; #1 rstn = 1; #1 source = 1; ..